The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, improvement in device driving current is becoming more important. Device current is closely related to gate length, gate capacitance, and carrier mobility. Shortening poly-gate length, increasing gate capacitance, and increasing carrier mobility can improve the device current performance. Gate length reduction to shrink circuit size is an on-going effort. Increasing gate capacitance has also been achieved by efforts such as reducing the gate dielectric thickness, increasing the gate dielectric constant, and the like. In order to further improve device current, enhancing carrier mobility has also been explored.
Among efforts made to enhance carrier mobility, forming a strained silicon channel is a known practice. Strain, sometimes referred to as stress, can enhance bulk electron and hole mobility. The performance of a MOS device can be enhanced through a strained-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
When silicon is placed under strain, the in-plane, room temperature electron mobility is dramatically increased. One way to develop strain is by using a graded SiGe epitaxy layer as a substrate on which a layer of relaxed SiGe is formed. A layer of silicon is formed on the relaxed SiGe layer. MOS devices are then formed on the silicon layer, which has inherent strain. Since the lattice constant of SiGe is larger than that of Si, the Si film is under biaxial tension and thus the carriers exhibit strain-enhanced mobility.
Strain in a device may have components in three directions, parallel to the MOS device channel length, parallel to the device channel width, and perpendicular to the channel plane. The strains parallel to the device channel length and width are called in-plane strains. Research has revealed that a bi-axial, in-plane tensile strain field can improve nMOS performance, and compressive strain parallel to channel length direction can improve pMOS device performance.
Strain can also be applied by forming a strained capping layer, such as a contact etch stop (CES) layer, on a MOS device. When a strained capping layer is deposited, due to the lattice spacing mismatch between the capping layer and underlying layer, an in-plane stress develops to match the lattice spacing. FIG. 1 illustrates a conventional MOS device having a strained channel region. Strained capping layers, such as spacers 9 and CES layer 14, introduce a strain in source/drain regions 12 (including LDD regions 15), and a strain is generated in channel region 11. Therefore, the carrier mobility in the channel region 11 is improved.
The conventional method of forming strained capping layers suffers drawbacks, and the effect is limited by the properties of the capping layer. For example, the thickness of the strained capping layer is limited due to the subsequent gap filling difficulty caused by the thick capping layer. Therefore, the strain applied by the capping layer is limited. In addition, forming a strained capping layer that has customized strains for different devices, such as pMOS and nMOS devices, is particularly complex and costly. The process-induced strain significantly influences the transistor device performance. Many local mechanical stress-controlling techniques have been proposed to enhance the carrier mobility for better device performance. For example, highly strained silicon nitride layers have been used as contact etch stop layers or spacers to introduce strong strain in channel regions of transistors. All these methods will have limitations due to properties of the strained layer. It is difficult to deposit a high quality layer with high strain.
What is needed, then, is a method to improve a capping layer's ability to impose a strain to the channel region of the MOS device without adding more complexity into the manufacturing processes.